package cim144.ctdp_mul_shift

import chisel3._ // VecInit
import freechips.rocketchip.tile._
import freechips.rocketchip.config._
import freechips.rocketchip.diplomacy._ // LazyModule
import freechips.rocketchip.rocket._ //

class CIM144_ctdp_mul_shift(opcode: OpcodeSet)(implicit p: Parameters) extends LazyRoCC(opcode)  {
  override lazy val module = new CIM144_ctdpImp_mul_shift(this) {
  }
}
class CIM144_ctdpImp_mul_shift(outer: CIM144_ctdp_mul_shift)(implicit p: Parameters) extends LazyRoCCModuleImp(outer){
  val ctrl = Module(new CIMController()).io
  val dtpt = Module(new CIMDatapath()).io
  ctrl.busy <> io.busy
  //first  cmd  channel
  ctrl.cmd.valid <> io.cmd.valid
  ctrl.cmd.ready <> io.cmd.ready    //fan
  ctrl.cmd.funct <> io.cmd.bits.inst.funct
  ctrl.cmd.rs1   <> io.cmd.bits.rs1
  ctrl.cmd.rs2   <> io.cmd.bits.rs2
  // second mem channel
  ctrl.mem.req_valid <> io.mem.req.valid
  ctrl.mem.req_ready <> io.mem.req.ready
  ctrl.mem.req_addr  <> io.mem.req.bits.addr
  ctrl.mem.req_cmd   <> io.mem.req.bits.cmd
  ctrl.mem.req_data  <> io.mem.req.bits.data
  ctrl.mem.resp_valid<> io.mem.resp.valid
  ctrl.mem.resp_data <> io.mem.resp.bits.data
  io.mem.req.bits.size := 3.U
  // ctrl to dathpath
  dtpt.ctl <> ctrl.ctl
  ctrl.dtp <> dtpt.dtp
}


class WithCIM144_ctdp_mul_shift extends Config((site,here,up) => {
  case BuildRoCC => Seq(
    (p:Parameters) => {
      //val regBufferNum = 128 // RoCC buffer numer
      val cim144 = LazyModule(new CIM144_ctdp_mul_shift(OpcodeSet.custom0)(p))
      cim144
    }
  )
})